In display devices, there are arranged a TFT substrate and an opposite substrate. The TFT substrate has pixels which are formed in matrix and each of which has a pixel electrode and a thin film transistor (TFT). The opposite substrate is opposed to the TFT substrate, and has a color filter or the like in a position corresponding to the pixel electrode of the TFT substrate. In liquid crystal display devices, liquid crystal is sandwiched between the TFT substrate and the opposite substrate. Light transmittance by liquid crystal molecules is controlled in association with each pixel, thereby forming images.
In recent years, along with the rapid diffusion of Smart Phones (registered trademark) or tablet devices, there are high demands for high refinement, power consumption reduction, and cost reduction in the liquid crystal display (LCD) applied thereinto. To meet the demands, the development of oxide TFTs has been activated as TFT substrates in the LCD, using TAOS (Transparent Amorphous Oxide Semiconductors), particularly, IGZO (Indium Gallium Zinc Oxide) film as a channel layer (Japanese Unexamined Patent Application Publication No 2010-67849). Note that the TAOS has a higher mobility than amorphous Si (a-Si).
An object of Japanese Unexamined Patent Application Publication No 2010-67849 is to provide a thin film field effect transistor having a high mobility and a high ON/OFF ratio and also a display device using the transistor. As illustrated in FIG. 12, as one example, there is disclosed a thin film field effect transistor which has at least an insulating layer 502, a gate electrode 503, a gate insulating film 504, an activate layer 505, a source electrode 507-1, and a drain electrode 507-2, on a substrate 501. The active layer 505 is an oxide semiconductor layer. A resistive layer 506 formed of an oxide semiconductor layer is provided between the activate layer 505 and at least one of the source electrode 507-1 and the drain electrode 507-2. The electric conductivity of the active layer 505 is 10−4 Scm−1 or greater but less than 102 Scm−1. The ratio of the electric conductivity of the active layer 505 to the electric conductivity of the resistive layer 506 (electric conductivity of the active layer/electric conductivity of the resistive layer) is 101 or greater or 1010 or below. One side of at least one of the source electrode and the drain electrode in contact with the resistive layer 506 is Ti or a Ti alloy layer. A reference numeral 510 denotes an overlapped region of the gate electrode with the source electrode or the drain electrode.
Because oxide semiconductors have a higher mobility than a-Si, it is estimated that they will take the place of a-Si from this time on. The inventors have examined the oxide semiconductors in detail. From the findings, (1) the electron field-effect mobility in the amorphous Si (a-Si) TFT is very low, that is, up to 1 cm2/Vs. If the TFT size is reduced, insufficient writing to pixels occurs. It is difficult to reduce the TFT size for high refinement. For example, in the IGZO-TFT, the electron field-effect mobility is large, that is, up to 10 cm2/Vs. Thus, even in a small-sized TFT, the wiring into the pixels is performed in safe, thus enabling to improve the refinement. (2) A leakage current occurs, even a gate voltage is OFF, in the conventional low-temperature polysilicon TFT (LTPS-TFT) or a-Si TFT. At this time, holding of a pixel voltage is the subject matter to be solved, when the TFT is not selected. The off-leak current is lower in the IGZO-TFT than in the LTPS-TFT by three digits, and lower than in the a-Si TFT by two digits. Therefore, a holding voltage of the pixel is easily reduced.
(i) The IGZO film is weak against hydrogen, and hydrogen deficiency easily occurs. There is a concern about the long-term stability. (ii) If a gate negative stress is applied to the IGZO-TFT under light emission, a threshold value voltage (Vth) easily shifts along with the applied time of the stress. The Vth shift has a negative influence on the operation or display of the panel. (iii) Due to the problem of the Vth shift, the IGZO film is shielded from backlight. Thus, a gate shielding structure is often applied into the TFT with a bottom gate structure (inversely-staggered type). However, in this structure, parasitic capacitances (Cgd, Cgd) increase between the gate electrode and the source/drain electrode. This easily results in some problems. That is, the punch-through voltage of the pixel increases so as to generate a flicker on the panel display, and the driving performance of the peripheral circuit decreases.
For the above-described problems (ii) and (iii), to reduce the parasitic capacitances Cgs and Csd of the bottom gate TFT having the gate electrode shielding structure, it is preferred to reduce overlapped regions (regions denoted by the reference numeral 510 of FIG. 12) of the gate electrode and the source/drain electrode. However, in fact, this is very difficult in view of light diffusion or the manufacturing margin. Thus, in a realistic method, the film thickness of the IGZO is increased, and the distance between the gate electrode and the source/drain electrode is increased in a longitudinal direction. Based on a consideration of the above-described problem (i), it is effective to cover the oxide semiconductor layer as a channel layer with a channel protection film.
In FIG. 12, an original oxide TFT has been manufactured. In this TFT, the channel layer (active layer) 505 is made thick, and a channel protection layer is provided between the channel layer 505 and the resistive layer 506. However, it is ascertained that, in this oxide TFT, the initial Vth is easily depleted. Based on the inventors' examination results, in the TFT having the channel protection layer, oxygen deficiency easily occurs on the back channel side of the IGZO film, due to the damage at the film formation of the channel protection layer using plasma CVD. After escape of oxygen, a surplus of electrons behaves as carriers. In the IGZO-TFT, it is estimated that an initial threshold value voltage (Vth) is easily depleted. As a result of the Vth depletion, the operation of the peripheral circuit is difficult, if there is any peripheral circuit incorporated in the panel. As a result of further examination, it is effective that the IGZO film of the channel layer is made thin, in a method for suppressing the depletion of the Vth. In the TFT with the bottom gate structure, the reason is that the backchannel side of the IGZO film is easily controlled in accordance with a gate voltage. In addition, when the voltage is negative, the energy band in the backchannel is not likely to be decreased, and the electrons are not easily induced. However, if the film thickness of the IGZO film of the channel layer is made thin, the parasitic capacitance Cgs or Csd of the bottom gate TFT increases. That is, there is a trade-off between the directions of measures for the thickness of the IGZO film.
In Japanese Unexamined Patent Application Publication No 2010-67849, no consideration is given at all to a problem and its measure in a case where a channel protection film is formed for protecting the channel layer on the oxide semiconductor layer as a channel layer, and also measures for attaining both suppression of Vth depletion and reduction of the parasitic capacitances (Cgs, Cgd).